Principal Engineer – Design

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Job Description

• To lead technically in ASIC design implementation domain, which may include stages from design architectural understanding till timing signoff for tapeout
• To develop and signoff I.C. design projects RTL2GDS implementation and flow improvement.
  
  

Responsibilities Include (as Applicable)

• Architectural and micro-architectural intent understanding
• RTL design structure for effective and efficient synthesis implementation
• Derive timing constraints from design spec, review and validate with respective designer/architect for signoff
• Design-For-Test (DFT) implementation, covering basic scan insertion, compression, LOC/LOS, RAMBIST all the way to advanced handling for performance/schedule/coverage trade-off
• Low power design; starting from architectural feedback, vector-driven synthesis/layout optimization and leakage/dynamic power control techniques
• Provide technical guidance and review for team members in solving complex challenges, with high problem-solving skill and critical thinking capability
• Creating technical intellectual property such as patents and trade secrets
• Drive for Best-in-Class design implementation approach/process or new design methodologies benchmarking
  
  

To document I.C. Design implementation and work procedures

• Capturing design implementation approach, consideration, challenges and solutions employed using corporate template documentation
• Complete audit and checklist fill-in, review and closure in compliance to corporate Design Control Procedures (DCP)
• Filing issues, solution details and review confirmation in project ticketing system (PEPS) or CAD ticketing system (JIRA)
  
  

To interface with

• Project manager, product-development and ATPG team on project related issues
• CAD/TA on flow methodology
  
  

Requirements/Qualifications

• Bachelor’s/Master’s Degree in Electrical/Electronics Engineering, with 12-16 years of ASIC I.C. Design working experience
• Cadence Genus or Synopsys DesignCompiler expertise
• Cadence Tempus or Synopsys Primetime expertise
  
  

Added advantage

• Exposure to 7nm and below advanced process nodes
• Familiar with System-Verilog foundation and coding
• Strong scripting skills in Perl, TCL, Shell or Python
  
  

Travel Time

0% - 25%

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