Process Engineer (Die Location Check)

OUR STORY

At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.

When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.

Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.

Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

YOUR ROLE

We are seeking a highly motivated DLC Engineer to support and optimize die location verification processes in semiconductor manufacturing. The successful candidate will play a key role in ensuring accurate die mapping, alignment, and defect localization to support high-quality, stable, and efficient production.

• Operate and optimize die location inspection systems (e.g., automated optical inspection, die sorters, or alignment tools) by defining and tuning inspection recipes to ensure precise die coordinate verification and defect placement accuracy.
• Perform routine process monitoring and troubleshooting, including tool qualification, SPC tracking for alignment parameters, and image-based defect analysis, to maintain stable and repeatable die location accuracy.
• Analyze die location and metrology data to identify misregistration trends, conduct root-cause analysis, and implement corrective and preventive actions (CAPA) to enhance yield, throughput, and process stability.
• Update die location process spec and Work Instruction (WI) to reflect process changes and improvements.
• Collaborate closely with cross-functional teams including APL, Production, QA, and equipment engineers to resolve die placement or mapping discrepancies.
• Participate actively in team meetings and problem-solving discussions, providing support to shift engineers and technicians on DLC-related issues.
• Engage in continuous improvement initiatives to enhance die location inspection efficiency, yield, and quality, including identifying and implementing opportunities for automated die mapping and alignment verification.

YOUR SKILLS & EXPERIENCES

• Minimum bachelor’s degree in Physics / Chemistry / Material Science/ Mechanical / Electronic or Electrical Engineering or equivalent.
• Knowledge on semiconductor process technology.
• Possess strong technical competencies in his field of study.
• Good knowledge of statistical and quality tools.
• Able to work under pressure and with strong commitment at work.
• Experience with software applications such as MS Power Point, Excel and Word.
• Experience with Lithography tools (Optional)

ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.

To discover more, visit st.com/careers.